CCD Long-Time Delay Line.

Abstract

A low-loss mode for operating CCDs is described that should lead to a decrease of the transfer losses in long CCD structures by more than two orders of magnitude. The analysis indicates that a buried-channel CCD operating in the low-loss mode should have an effective transfer loss of less than 10 to the -7th power per transfer. This report also describes the design of a low-loss CCD test chip containing 256- and 1024-stage, closed-loop CCDs. Operating as low-loss CCDs, these devices can store and recirculate 128 and 512 signal samples, respectively. The closed-loop CCD structures include a provision for adding input signal to the signal already present in the loop. In addition to the low-loss signal regeneration stages (one in the smaller loop and two in the larger loop), each closed-loop CCD also includes two floating-gate outputs for nondestructive output sensing, a floating-diffusion output for a destructive readout, and a dark-current subtraction stage. Also described in the report is the design of a programmable tester for operating the closed-loop CCDs on the low-loss CCD test chip. (Author)

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Document Details

Document Type
Technical Report
Publication Date
Nov 01, 1978
Accession Number
ADA063800

Entities

People

  • D. J. Sauer
  • W. F. Kosonocky

Organizations

  • RCA Corporation

Tags

Communities of Interest

  • Advanced Electronics
  • Materials and Manufacturing Processes

DTIC Thesaurus Topics

  • Air Force
  • Amplifiers
  • Charge Carriers
  • Charge Coupled Devices
  • Charge Transfer
  • Circuits
  • Construction
  • Delay Lines
  • Demographic Cohorts
  • Diffusion
  • Dual Channel
  • Dynamic Range
  • Electronics
  • Electrons
  • Frequency
  • Shot Noise
  • Waveforms

Readers

  • Control Systems Engineering.
  • Image Processing and Computer Vision.
  • Integrated Circuit Design and Technology.