Ion Implanted GaAs I.C. Process Technology

Abstract

This report covers a program on the development of a planar GaAs digital integrated circuit (IC) technology. The main goals of this program were the development and implementation of the fabrication technology, and the demonstration of the feasibility of reaching large-scale integration (LSI) with high-speed, low-power GaAs digital ICs. In approximately 3 1/2 years a planar fabrication process was developed and refined. The program started with the fabrication of the first planar FET transistors using the new process, and the demonstration of Schottky diode-FET logic (SDFL) gates, showing high speed operation of ring oscillators. After this initial stage, many logic circuits have been built. The complexity of these demonstration circuits, involving both combinatorial and sequential logic, grew at a nearly exponential rate. Among the most complex circuits fully demonstrated is a 5 x 5 bit parallel multiplier employing 260 SDFL gates.

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Document Details

Document Type
Technical Report
Publication Date
Jul 01, 1981
Accession Number
ADA104946

Entities

People

  • B. M. Welch
  • F. H. Eisen
  • F. S. Lee
  • P.M. Asbeck
  • R. Zucca
  • S. I. Long

Tags

Communities of Interest

  • Advanced Electronics

DTIC Thesaurus Topics

  • Ceramic Materials
  • Circuit Analysis
  • Electrical Properties
  • Fabrication
  • Field Effect Transistors
  • Integrated Circuits
  • Large Scale Integration
  • Logic Gates
  • Manufacturing
  • Mass Spectrometry
  • Materials Science
  • Schottky Diodes
  • Semiconductor Manufacturing
  • Semiconductors
  • Statistical Analysis
  • Two Dimensional
  • Very Large Scale Integration

Readers

  • Integrated Circuit Design and Technology.
  • Semiconductor Device Technology