Design and Development of a Multipin SGEMP Current Injection Test Technique
Abstract
Verification tests are imposed by satellite system survivability specifications which require that an SGEMP current injection test be performed on each Qualification Level Component Box to demonstrate SGEMP hardness. This report represents the results of an extensive analytical and computational evaluation of the response of termination loads to cable SGEMP signals driven in multiwire cable bundles, and the design, development and experimental verification of a Multipin Current Injection Test (C.I.T.) Method for performing SGEMP hardness verification tests on electronic component boxes. This C.I.T. method was developed to meet the technology needs for user-0riented current injection technique using realistic hardware to correctly perform these SGEMP electrical simulation tests at the individual component box level as well as at the subsystem and system levels. The purpose of the analytical development work was to quantify the dependence of the termination response on the manifold of parameters which specify the cable SGEMP threat in choice of the drive levels, coupling factors, and cable characteristic impedances required in the implementation of this test technique.
Document Details
- Document Type
- Technical Report
- Publication Date
- Jun 01, 1982
- Accession Number
- ADA130932
Entities
People
- B. Beers
- D. Tasca
- H. O'donnell
- J. Klisch
- J. Peden
- J. Tigner
Organizations
- General Electric