The Design and Layout of a Complementary Metal Oxide Semiconductor Silicon on Sapphire Cell Library.

Abstract

A method was developed for designing CMOS/SOS circuits using computer-aided design tools. CMOS/SOS fabrication methods and theory of operation as well as differences between CMOS/SOS and bulk CMOS were researched. SPICE was used to determine optimum gate width-to-length ratios resulting in symmetrical transitional delays. Two designs were developed to implement the CMOS/SOS programmable logic array (PLA), and a C program was written to automatically generate one of the designs by means of a file formatted in Caltech Intermediate Form (CIF). Basic logic gates were designed as part of a small CMOS/SOS standard cell library, and a medium scale integration (MSI) arithmetic logic unit (ALU) was developed using cells from the library. An analysis was made of significant differences between a NMOS PLA developed by Standford and the CMOS/SOS PLA. According to SPICE results, the CMOS/SOS PLA exhibited slightly faster switching speeds and greatly reduced power dissipation. CMOS/SOS circuits required significantly larger layouts than similar NMOS circuits.

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Document Details

Document Type
Technical Report
Publication Date
Dec 01, 1983
Accession Number
ADA138310

Entities

People

  • W. E. Sommars

Organizations

  • Air Force Institute of Technology

Tags

Communities of Interest

  • Advanced Electronics

DTIC Thesaurus Topics

  • Birds
  • Complementary Metal-Oxide Semiconductors
  • Computer Programs
  • Computer-Aided Design
  • Computers
  • Electronics Industry
  • Electronics Laboratories
  • Fabrication
  • Integrated Circuits
  • Logic Gates
  • Metal Oxide Semiconductors
  • Metal Oxides
  • Modules (Electronics)
  • Operating Systems
  • Semiconductor Devices
  • Semiconductors
  • Standards

Fields of Study

  • Physics

Readers

  • Integrated Circuit Design and Technology.
  • Mathematics or Statistics

Technology Areas

  • Microelectronics