Comparative Architectures for a Multiple Function Speech Processor.
Abstract
A study of the feasibility of realizing a compact, multiple function speech processor using digital signal processing integrated circuits is presented in this report. The processor is required to accommodate a 2400 bps Linear Predictive (LPC-10) vocoder, a 9600 bps Adaptive Predictive (APC) vocoder, and wireline modems at the corresponding data rates. Architectures employing the Texas Instruments TMS32010 and the Fujitsu MB8764 digital signal processing integrated circuits appeared to be most likely to achieve this goal. Since the current generation of DSP chips does not permit the algorithms to be contained in a processor simultaneously, the study was confined to the realization of each of the functions individually using replaceable ROMs. A proposed architecture based on the TMS32010 includes automatic address generation hardware to permit fast processing of large blocks of data stored in external memory. Although specifically tailored to implement the Adaptive Predictive Coding algorithm, the processor appears to be a likely candidate for the multiple function task as well. An architecture based on the MB8764 includes special purpose hardware which adds an interrupt capability to the device. A detailed study of the Fujitsu-based design indicates that a compact realization of the multiple function processor can be realized using commercially available hardware and a custom IC fabricated using in-house design tools.
Document Details
- Document Type
- Technical Report
- Publication Date
- Dec 18, 1984
- Accession Number
- ADA150873
Entities
People
- E. Singer
Organizations
- Massachusetts Institute of Technology