A Parallel Stack Processor To Reduce Procedure-Call Overhead.

Abstract

A processor organization is presented to reduce the large overhead of procedure calls in high-level languages. In the Parallel Stack Processor, processor registers are each at the top of a hardware stack of registers. Saving processor registers on procedure call takes place in one cycle by pushing all registers simultaneously. A detailed performance model, driven by dynamic high-level language statistics, is presented. Results from the model indicate the effect on performance of the parallel stack computer architecture when compared to a processor without parallel stacks. The processor architecture is specified in the report along with a discussion of implementation details for the VLSI single-chip processor. Keywords: Parallel processors; Stacking; and Reduced Instruction Set Computer. (Author)

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Document Details

Document Type
Technical Report
Publication Date
Nov 01, 1985
Accession Number
ADA162494

Entities

People

  • Richard J. Eickemeyer

Organizations

  • University of Illinois Urbana–Champaign

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  • Advanced Electronics

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  • Assembly Languages
  • C Programming Language
  • Coding
  • Computer Architecture
  • Computer Programming
  • Computer Programs
  • Computers
  • Computing System Architectures
  • Decoding
  • Electrical Engineering
  • Engineering
  • High Level Languages
  • Instruction Set Architecture
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  • Operating Systems
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  • Computational Linguistics
  • Parallel and Distributed Computing.