Arithmetic Circuitry for High Speed VLSI Winograd Fourier Transform Processor.

Abstract

The objective of this thesis is to define, design, and implement an efficient VLSI architecture which computes the Discrete Fourier Transform using the Winograd Fourier Transform Algorithm. The architecture includes circuitry to perform input/output, WFT calculations, parity checking and generation, and scale factor generation. Keywords: Chips(Electronics); Digital Signal processing.

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Document Details

Document Type
Technical Report
Publication Date
Dec 01, 1985
Accession Number
ADA163943

Entities

People

  • Paul W. Coutee

Organizations

  • Air Force Institute of Technology

Tags

Communities of Interest

  • Advanced Electronics
  • Energy and Power Technologies
  • Space

DTIC Thesaurus Topics

  • Accuracy
  • Air Force
  • Algorithms
  • Arithmetic
  • Complementary Metal-Oxide Semiconductors
  • Computing System Architectures
  • Digital Signal Processing
  • Discrete Fourier Transforms
  • Electrical Engineering
  • Energy Consumption
  • Engineering
  • Fault Tolerance
  • Logic Gates
  • Semiconductors
  • Signal Processing
  • Test Methods
  • Xor Gates

Fields of Study

  • Engineering

Readers

  • Approximation Theory.
  • Computer Science/Computer Engineering/Data Science/Digital Signal Processing.
  • Parallel and Distributed Computing.

Technology Areas

  • Microelectronics