LSI/VLSI Ion Implanted GaAs IC (Integrated Circuits) Processing
Abstract
This report covers the first quarter of a program aimed at fully realizing the potential of GaAs for digital integrated circuits employing depletion mode MESFETs. The highlight of this first quarter is the successful operation of the 8 x 8 bit parallel multiplier having 1008 gates, fabricated from mask AR5 of a previous ARPA program. This result completes the demonstration of the feasibility of high-speed low-power LSI (>1000 gates) GaAs digital integrated circuits. The multiply time of this circuit 5.2 ns, exceeds by for the performance of currently available multipliers. Other highlights of this first quarter are the successful fabrication and operation of circuits on substrate wafers grown by the liquid encapsulated Czochralski (LEC) technique, the material which is today capable of producing the large diameter wafers required by this program. Investigation of circuit reliability has begun. While successful operation at 125 deg for a moderate period of time (140 hrs) was demonstrated, degradation observed at temperatures above 200 deg has been traced to ohmic contact reliability. Intensive studies of the ohmic contact metalization schemes are under consideration. Promising results from radiation hardness experiments have been obtained. The demonstration circuits to be incorporated in the first mask set have been identified, and their design and layout has begun.
Document Details
- Document Type
- Technical Report
- Publication Date
- Feb 01, 1981
- Accession Number
- ADA186522
Entities
People
- A. Firstenberg
- F. S. Lee
- P.M. Asbeck
- R. Zucca
- S. I. Long