Architecture of a Message-Driven Processor,

Abstract

We propose a machine architecture for a high-performance processing node for a message-passing, MIMD concurrent computer. The principal mechanisms for attaining this goal are the direct execution and buffering of messages and a memory-based architecture that permits very fast context switches. Our architecture also includes a novel memory organization that permits both indexed and associative accesses and that incorporates an instruction buffer and message queue. Simulation results suggest that this architecture reduces message reception overhead by more than an order of magnitude.

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Document Details

Document Type
Technical Report
Publication Date
Nov 01, 1987
Accession Number
ADA195431

Entities

People

  • A. Chien
  • Leon Chao
  • S. Hassoun
  • W. Horwat
  • W. J. Dally

Organizations

  • Massachusetts Institute of Technology

Tags

Communities of Interest

  • Energy and Power Technologies

DTIC Thesaurus Topics

  • Arithmetic
  • Arithmetic Units
  • Artificial Intelligence
  • Computer Architecture
  • Computer Programming
  • Computer Programs
  • Computer Science
  • Computers
  • Computing System Architectures
  • Grain Size
  • Instruction Set Architecture
  • Models
  • Network Protocols
  • Networks
  • Object Oriented Programming
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Fields of Study

  • Computer science

Readers

  • Parallel and Distributed Computing.