Design and Implementation of a CMOS Chip for a Prolog

Abstract

A high performance VLSI chip for executing Prolog programs is designed and fabricated using a 1.4 micron CMOS technology with two layers of metal. This chip implements a tagged architecture with hardware support for five stacks. The 32-bit data path of the chip contains a fast ALU, 64 registers in four groups, five counters, and six non-master/slave registers. The control is microprogrammed and uses a 512 x 160 bit ROM with four pages for fast microbranching. The chip operates at a cycle time of 100 ns (worst case) and has a size of 10 mm x 9 mm. A semicustom design methodology employing Mentor and NCR tools has been used in this design. The challenges involved in the design, verification, routing, and fabrication of the chip are described. Keywords: Very large scale integration; Integrated circuits; Complementary metal oxide semiconducting; Arithmetic logic unit.

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Document Details

Document Type
Technical Report
Publication Date
Mar 01, 1988
Accession Number
ADA198304

Entities

People

  • Bruce K. Holmer
  • Jerric V. Tam
  • S. L. Graham
  • Tam M. Nguyen
  • Vason P. Srini

Organizations

  • University of California, Berkeley

Tags

Communities of Interest

  • Advanced Electronics

DTIC Thesaurus Topics

  • Abstracts
  • Artificial Intelligence
  • California
  • Classification
  • Computer Programming
  • Computer Science
  • Computers
  • Computing System Architectures
  • Data Transmission
  • Diagrams
  • Fabrication
  • Instruction Set Architecture
  • Integrated Circuits
  • Microelectromechanical Systems
  • Simulations
  • Simulators
  • Very Large Scale Integration

Fields of Study

  • Engineering

Readers

  • Integrated Circuit Design and Technology.
  • Parallel and Distributed Computing.