Architecture and Design for a Laser Programmable Double Precision Floating Point Application Specific Processor
Abstract
Numerous signal processing systems in the Department of Defense and industry would benefit from a microprocessor tailored to their specific applications. This thesis effort describes the architecture and design for a 64 bit application specific processor (ASP) which combines the power of double precision floating point hardware with the flexibility of a laser programmable microcode store. This floating point ASP (FPASP) contains a variety of circuits which efficiently perform digital signal processing and other applications requiring double precision floating point arithmetic. This thesis describes a new rapid prototyping methodology for ASPs. The user provides an algorithm which is translated into microcode, tested on a software model, and then cut into the laser PROM of a blank FPASP chip. With this methodology the prototyping of an ASP can be completed in a matter of days, and no hardware design is involved. The programmed FPASP can then be mounted on a circuit board and placed in a host processor to act as a hardware accelerator for computationally intense programs. The FPASP also supports a macro assembly language which can be partially user- defined. So the FPASP can be tailored to higher level applications such as operating system support. Keywords: Computer architecture; Very large scale integration; Problem solving.
Document Details
- Document Type
- Technical Report
- Publication Date
- Dec 01, 1988
- Accession Number
- ADA202560
Entities
People
- John H. Comtois
Organizations
- Air Force Institute of Technology