On-Line Arithmetic Algorithms and Structures for VLSI

Abstract

The research and development problem we have investigated in this project is the VLSI implementation of fast and highly parallel algorithms based on one-line arithmetic. The on-line approach is characterized by simple interconnection requirements and digit-level pipelining suitable for highly concurrent special-purpose VLSI designs. The objective of the project was to evaluate the feasibility and efficiency of on-line approach in NMOS and CMOS VLSI implementations (B) bit-level design and simulation, (C) NMOS and CMOS circuit-level design and simulation, (D) VLSI chip implementation, (E) performance measurements and evaluation, (F) development of design methodologies for special-purpose arithmetic-intensive architectures, and (G) applications of on-line/redundant algorithms to signal processing and matrix computations.

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Document Details

Document Type
Technical Report
Publication Date
Nov 01, 1988
Accession Number
ADA203421

Entities

People

  • Miloes D. Ercegovac
  • Tomas Lang

Organizations

  • University of California, Los Angeles

Tags

Communities of Interest

  • Advanced Electronics
  • C4I
  • Materials and Manufacturing Processes

DTIC Thesaurus Topics

  • Algorithms
  • Arithmetic Units
  • Biodiesels
  • Computations
  • Computer Programming
  • Computer Science
  • Computers
  • Data Transmission
  • Electrical Engineering
  • Linear Arrays
  • Military Research
  • Parallel Computing
  • Parallel Processing
  • Signal Processing
  • Standards
  • Two Dimensional
  • Very Large Scale Integration

Fields of Study

  • Engineering

Readers

  • Integrated Circuit Design and Technology.
  • Parallel and Distributed Computing.