A Unified Approach to the Synthesis of Fully Testable Sequential Machines
Abstract
In this paper we attempt to unify and extend the various approaches to synthesizing fully testable sequential circuits that can be modeled as finite state machines (FSMs). We first identify classes of redundancies and isolate equivalent-state redundancies as those most difficult to eliminate. We then show that the essential problem behind equivalent-state redundancies is the creation of valid/invalid state pairs. We devote the remainder of the paper to techniques for developing differentiating sequences for valid/invalid state pairs created by a fault, as well as to techniques for retaining these sequences in the presence of that fault. A variety of techniques have been proposed to address this problem. At one end of the spectrum there are optimal synthesis procedures that ensure full testability by eliminating redundancies via the use of appropriate don't care sets. At the other end of the spectrum there are constrained synthesis procedures that produce fully and easily testable sequential circuits by restricting the implementation of the logic. The optimal synthesis procedures require fewer constraints on the logic but increase the expense of logic optimization to the point that CPU time requirements may be unacceptable. The constrained synthesis procedures require relatively simple logic optimization procedures but constrain the logic to the point that the area penalty may be unacceptable.
Document Details
- Document Type
- Technical Report
- Publication Date
- Oct 01, 1989
- Accession Number
- ADA217120
Entities
People
- Kurt Keutzer
- Srinivas Devadas
Organizations
- Massachusetts Institute of Technology