Estimation of a Photon Budget for the Upper Ocean in the Sargasso Sea
Abstract
The major results are in two areas -- Studies of systematic design procedures for a class of structured algorithms often encountered in signal processing applications. These are being called Regular Iterative Algorithms (RIAs). These ideas have been successfully used by a former student who helped this theory, Dr. S. K. Rao of AT&T Bell Laboratories in Holmdel, N.J. Dr. Rao has found the RIA results helpful in designing several fast integrated circuit chips for communications and signal processing applications, some of which are being used in the AT&T - ZENITH joint effort on High Definition Television (HDTV) . The other set of results deals with the issue of designing configurable and fault tolerant processor arrays such that if some of the processors in the given array are faulty, then a fault free array can be constructed comprising only the healthy processors. Such studies can be easily motivated in the case of Wafer Scale Integration (WSI) technology where for example, a large number of processors, configured in the form of a grid, can be put on a single wafer. Due to yield problems, some of the processors are invariably going to be faulty. In such a case, instead of treating the whole wafer as defective, one can work around the faulty processors and reconfigure the rest in the form of a grid.
Document Details
- Document Type
- Technical Report
- Publication Date
- Jan 01, 1989
- Accession Number
- ADA226023
Entities
People
- E. Swift
- John Marra
- K. S. Baker
- M. J. Perry
- R. C. Smith
Organizations
- University of California, Santa Barbara