ICHARM: Hierarchical CMOS Circuit Extraction with Power Bus Extraction

Abstract

Circuit extraction is critical in the validation of VLSI circuits since it provides the link between the design and the simulation phases. The use of hierarchical design techniques and hierarchical analysis methods increases design productivity. In this thesis, the development of iCHARM, a hierarchical circuit extractor, is described. The extractor takes its input layout in either the CIF format or the Oct VLSI database format. The extractor produces circuit parasitics including capacitances and resistances. A power bus extraction mode has been developed to calculate power bus currents for reliability estimation. The primary contribution of this work is a method to extract a circuit hierarchically without flattening and with minimal overhead. A full-chip layout was used to test the extractor's functionality and to allow a comparison of the hierarchical and flat extraction modes. (rh)

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Document Details

Document Type
Technical Report
Publication Date
Sep 05, 1990
Accession Number
ADA228613

Entities

People

  • Russell M. Iimura

Organizations

  • University of Illinois Urbana–Champaign

Tags

Communities of Interest

  • Energy and Power Technologies

DTIC Thesaurus Topics

  • Air Force
  • Batch Processing
  • Capacitance
  • Circuits
  • Computer-Aided Design
  • Computers
  • Databases
  • Generators
  • Geometry
  • Identification
  • Language
  • Lists (Data Structures)
  • Logic Gates
  • Networks
  • Operating Systems
  • Reliability
  • Standards

Readers

  • Database Systems and Applications
  • Integrated Circuit Design and Technology.