Floating Gate Circuits in MOSIS

Abstract

The MOSIS foundry offers a two-poly CMOS process that can be used as a floating gate technology, albeit not with the same performance as commercial EEPROM foundries. This report characterizes the structures and programming techniques necessary to build floating gate structures and associated high-voltage addressing circuitry on the low-noise analog process available through MOSIS. Techniques that are used include Fowler-Nordheim tunneling, channel hot-electron injection, and avalanche injection. The dielectric materials between the floating gate and both the control gate and substrate are characterized. Unconventional lightly doped drain FET devices and additional circuit techniques for handling the high-voltage programming signals are presented. (Author)

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Document Details

Document Type
Technical Report
Publication Date
Nov 01, 1990
Accession Number
ADA230154

Entities

People

  • James R. Mann

Organizations

  • Massachusetts Institute of Technology

Tags

DTIC Thesaurus Topics

  • Addressing
  • Bipolar Junction Transistors
  • Capacitance
  • Capacitors
  • Computer Programming
  • Dielectrics
  • Electric Fields
  • Electrons
  • High Voltage
  • Low Noise
  • Materials
  • Neural Networks
  • Noise
  • Quantum Tunneling
  • Substrates
  • Tunneling
  • Voltage

Fields of Study

  • Engineering

Readers

  • Integrated Circuit Design and Technology.

Technology Areas

  • Microelectronics