Failure Mechanisms in GaAs ICs: The Effects of Deep Traps
Abstract
GaAs FETs, 1 x 150 micron and 100 x 400 micron, were subjected to accelerated stress tests. The samples were of two types; with and without a burried p-layer. The life tests were of two types: a storage test at 250C; and a DC-biased life test at 225-235C. The FETs were characterized prior to and during the life tests using DLTS, I V characteristics, C-V profiling, Drift Mobility profiling, and backgating. Buried p devices degraded more slowly initially. There is substantial loss of carriers and significant degradation of the drift mobility. There is substantial loss of carriers and significant degradation of the drift mobility. The concentration of EL2 was seen to increase near the device surface, and a new trap emerged near the end of the life tests with an energy in the 0.6 - 0.7 range. Recommendations for further work are included. (Author)
Document Details
- Document Type
- Technical Report
- Publication Date
- Oct 01, 1991
- Accession Number
- ADA243013
Entities
People
- Paul A. Martin
Organizations
- General Electric