An Investigation of a Design for a Finite-Difference Time Domain (FDTD) Hardware Accelerator
Abstract
This study investigated increasing the speed of Finite-Difference Time Domain (FDTD) cell calculations through a special purpose architecture using Very Large Scale Integration (VLSI). These FDTD cell equations model inhomogeneous, isotropic, lossy magnetic and dielectric materials. Special attention was given to simplicity and performance, using the fastest components generally available in AFIT VLSI programs, while attempting to minimize component count. A VHSIC Hardware Description Language simulation of the proposed chip established design feasibility and provided performance estimates: 350 ns to generate the first cell value, 200 ns thereafter (30 MFLOPS maximum double-precision). This study also implemented boundary conditions in hardware as well. No new hardware was designed; instead, the algorithm was translated into microcode for use by the AFIT Floating Point Application Specific Processor. The first boundary value is computed in 850ns, with successive results calculated every 300 ns thereafter (43 MFLOPS maximum double-precision). Standard FDTD FORTRAN codes were run on a SPARC2 workstation and execution times compared to modified codes simulating the implementation of the above hardware. On a 66 cubic cell free-space computational domain, these chips reduced total FDTD code execution time by a factor of 4.9, and cell and boundary calculation time by a factor of 9.5.
Document Details
- Document Type
- Technical Report
- Publication Date
- Dec 01, 1991
- Accession Number
- ADA243823
Entities
People
- James R. Marek
Organizations
- Air Force Institute of Technology