Simulation of a Parallel Processor Based Small Tactical System
Abstract
The Simulation of A Parallel Processor Based Small Tactical System is a part of The Parallel Command and Decision System (PARCDS) Laboratory, which was established in early 1980's support research for the Navy's AEGIS combat system. Current U.S. Navy's AEGIS system using the standard AN/Uyk-7 computers, which has four processors in the computer system. When one of them fails, the system automatically reloads the remaining three processors with software that has a reduced capability. But in probably less than one decade, they will not be capable of handling the increasing demand for some more complex software systems. Military command and decision systems of the next decade must be characterized be economy, speed, stability, reliability, and ease of repair. The transputer features all of these benefits and provides a scalable network of transputers which is relatively easy to design. The need for parallel processing grows more evident daily, since the best high-performance uniprocessor architectures are reaching their limits. The prime objective of this thesis is to model a small tactical system by using a network of transputers to develop the transputer version of the Ada programming language system which models a small tactical system.
Document Details
- Document Type
- Technical Report
- Publication Date
- Dec 01, 1991
- Accession Number
- ADA245911
Entities
People
- Panurit Yuktadatta
Organizations
- Naval Postgraduate School