Automatic Digital Hardware Synthesis
Abstract
The automatic synthesis of a hardware description language (HDL) representation of a digital device has been the subject of significant research in the past five years. This thesis explores this topic as it applies to finite state machines and combinational logic expressed in a subset of the IEEE standard language VHDL (VHSIC Hardware Description Language). It describes the subset chosen, and the development of VHDL2PDS, a program which automates the process of translating VHDL to PALASM, a hardware synthesis language. The PALASM description is then directly implemented into a field programmable gate array (FPGA) using the Xilinx logic Cell Array (LCA) development system. Complete examples are provided which illustrate top-down design and testing using VHDL, and the use of software to produce a FPGA. This thesis demonstrates that selected constructs in VHDL can be automatically synthesized with a resulting savings in engineering development time due to the simplicity of this approach and the ease of verifying the correctness of the design.
Document Details
- Document Type
- Technical Report
- Publication Date
- Sep 01, 1990
- Accession Number
- ADA246976
Entities
People
- John W. Ailes
Organizations
- Naval Postgraduate School