Hardware-Verification Through Logic Extraction

Abstract

A Prolog-based system is described which employs logic-extraction to perform hardware-verification. The extraction rules are built automatically from hierarchical structural VHDL models, enabling the equivalence of a structural VHDL description and a layout specification to be verified. Pin-to-pin critical- path analysis is performed within the logic-extraction process; many noncritical paths are pruned early, making pin-to-pin critical path analysis of large circuits feasible. It is demonstrated that a design methodology based on logic extraction, VHDL, and a layout tool can provide a fabricated functionally- correct IC design without circuit-level or switch-level simulation. This methodology is shown to be practical for VLSI designs up to 250,000 transistors in size. The properties of correctness, completeness, and guaranteed termination are examined for the extraction process. VLSI, VHDL, Prolog, Circuit Extraction, Reverse Engineering, Computer Aided Design, Integrated Circuits, Artificial Intelligence.

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Document Details

Document Type
Technical Report
Publication Date
Mar 01, 1992
Accession Number
ADA248087

Entities

People

  • Michael A. Dukes

Organizations

  • Air Force Institute of Technology

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  • Advanced Electronics

DTIC Thesaurus Topics

  • Application-Specific Integrated Circuits
  • Artificial Intelligence
  • Circuit Analysis
  • Complementary Metal-Oxide Semiconductors
  • Computer Programs
  • Computer Science
  • Computer-Aided Design
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  • Digital Circuits
  • Engineering
  • Integrated Circuits
  • Language
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  • Semiconductor Devices
  • Simulations
  • Solid State Electronics
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  • Engineering

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  • Computational Linguistics
  • Integrated Circuit Design and Technology.
  • Software Engineering.

Technology Areas

  • AI & ML