Reliability Characterization of Digital Microcircuits - Investigation of an In-Process Oxide Reliability Screening Method

Abstract

This report covers the work performed, using a sacrificial-metal- pattern technique, to demonstrate a 100% in-process screen for oxide defects in high-density CMOS microcircuits, and to evaluate the effectiveness and side effects of the added processing steps on yield and reliability. Using large-area polysilicon capacitors and 101-stage metal-1 delay-lines in GEM WAT keys as test vehicles, experiments with split lot reliability screening and life test, first with 240 A and again with 150 A gate oxide, have demonstrated practically complete elimination of the defective populations for test capacitors and about 50% reduction in circuit functionality failures for delay-line circuits. This is accomplished with little or no penalty in metal-polysilicon contact resistance, or in delay-line circuit yield. The technique is found to be promising and should be further investigated with more complex circuits with double-level metals.... Oxide reliability, In-process screening effects, Voltage ramp oxide breakdown, Time-dependent dielectric breakdown, CMOS, CMOS-on-insulator, Integrated Circuits.

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Document Details

Document Type
Technical Report
Publication Date
Apr 01, 1993
Accession Number
ADA267053

Entities

People

  • Chung P. Wu

Tags

DTIC Thesaurus Topics

  • Charge Coupled Devices
  • Chemical Vapor Deposition
  • Command And Control
  • Computational Science
  • Crystal Structure
  • Delay Lines
  • Electronic Components
  • Electronics Laboratories
  • Fabrication
  • Failure Mode And Effect Analysis
  • High Density
  • Life Tests
  • Materials
  • Materials Science
  • Modules (Electronics)
  • Semiconductors
  • Test And Evaluation

Fields of Study

  • Engineering

Readers

  • Electrical Engineering
  • Integrated Circuit Design and Technology.
  • Phased Array Antenna Design.

Technology Areas

  • Microelectronics