Algorithms and Architectures for High Speed Signal Processing

Abstract

Issues related to designing configurable and fault-tolerant processor array such that even if some processors are faulty, a fault free array can be constructed using the healthy processors. The general models that have been explored consist of a set of identical processors embedded in a flexible interconnection structure that is configured in the form of a rectangular grid. In particular, models were studied that use multiple tracks along every grid line. Efficient scheduling algorithms were also developed for such processor arrays in the presence of communication delays. Configurable and fault-tolerant processor arrays, Wafer scale integration, Antenna array processing.

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Document Details

Document Type
Technical Report
Publication Date
Jul 31, 1993
Accession Number
ADA271000

Entities

People

  • Arogyaswami Paulraj
  • Thomas Kailath

Organizations

  • Stanford University

Tags

Communities of Interest

  • Energy and Power Technologies
  • Human Systems
  • Materials and Manufacturing Processes
  • Sensors

DTIC Thesaurus Topics

  • Algorithms
  • Antenna Arrays
  • Arrays
  • Bayesian Networks
  • Calibration
  • Computations
  • Computers
  • Direction Finding
  • Electrical Engineering
  • Engineering
  • Information Systems
  • Information Theory
  • Measurement
  • Military Research
  • Neural Networks
  • Probability
  • Signal Processing

Fields of Study

  • Engineering

Readers

  • Computer Programming and Software Development.
  • Microwave Engineering.
  • Software Engineering.

Technology Areas

  • AI & ML