Micro Benchmark Analysis of the KSR1.

Abstract

A new approach, micro benchmarks has recently been developed. Using this technique, we have analyzed the KSR1, and in particular the Allcache memory architecture and ring interconnection. We have been able to elucidate many facets of memory performance. The technique has enabled us to identify and characterize parts of the memory design not described by Kendall Square Research. Our results show that a miss in the local cache can incur a penalty ranging from 7.5 microseconds to 500 microseconds (when a dirty page in the local cache must be evicted). The programmer must be very careful in placement and accessing of data to obtain maximum performance from the KSR1; the data presented here will help in understanding the performance actually obtained. (AN)

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Document Details

Document Type
Technical Report
Publication Date
Nov 01, 1993
Accession Number
ADA293060

Entities

People

  • Michael J. Carlton
  • R. S. Gaines
  • Rafael H. Saavedra

Organizations

  • University of Southern California

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  • Energy and Power Technologies

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  • Parallel and Distributed Computing.
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