Analog Preprocessing in a SNS 2 Micrometers Low-Noise CMOS Folding ADC.

Abstract

Significant research in high performance analog-to-digital converters (ADCs) has been directed at retaining part of the high-speed flash ADC architecture, while reducing the total number of comparators in the circuit. The symmetrical number system (SNS) can be used to preprocess the analog input signal, reducing the number of comparators and thus reducing the chip area and power consumption of the ADC. This thesis examines a Very Large Scale Integrated (VLSI) design for a folding circuit for a SNS analog preprocessing architecture in a 9-bit folding ADC with a total of 23 comparators. The analog folding circuit layout uses the Orbit 2 micrometers CMOS N-well double-metal, double-poly low-noise analog process. The effects of Spice level 2 parameter tolerances during fabrication on the operation of the folding circuit are investigated numerically. The frequency response of the circuit is also quantified. An Application Specific Integrated Circuit (ASIC) is designed.

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Document Details

Document Type
Technical Report
Publication Date
Dec 01, 1994
Accession Number
ADA293356

Entities

People

  • Richard D. Carr

Organizations

  • Naval Postgraduate School

Tags

Communities of Interest

  • Advanced Electronics

DTIC Thesaurus Topics

  • Application-Specific Integrated Circuits
  • Circuit Analysis
  • Circuits
  • Complementary Metal-Oxide Semiconductors
  • Computer-Aided Design
  • Electrical Circuits
  • Energy Consumption
  • Fabrication
  • Frequency
  • Frequency Response
  • Integrated Circuits
  • Low Noise
  • Metal Oxide Semiconductors
  • Operational Amplifiers
  • Preprocessing
  • Semiconductors
  • Very Large Scale Integration

Fields of Study

  • Physics

Readers

  • Applied Combinatorial Optimization and Logic Circuit Design.
  • Integrated Circuit Design and Technology.

Technology Areas

  • Space