Fault Tolerance in Opto-Electronic Computing.
Abstract
In Fault Modeling and Testing of Complex Systems such as the opto-electronic computing systems, a probabilistic fault model for complex degradable system was proposed. This model has been validated by using an event-driven simulator and fault injector on the representative measures from both replicated and dilated multi-stage interconnection networks. Furthermore, an architecture which integrates the concept of concurrency and distributed test pattern generation for testing complex circuits on a planer layout has been proposed. This approach performs test pattern generation and response analysis concurrently, therefore minimizing testing time for the overall system testing. Circuits are partitioned into segments which can be tested in parallel in testing time bounded by 2 n clock cycles, where n is the maximum no. of inputs for the biggest cluster. The impact on the quality of the patterns generated has been found to be negligible. The software package is called Merced, which performs circuit test as well as performance analysis, with full compatibility with commercial tools.
Document Details
- Document Type
- Technical Report
- Publication Date
- Sep 01, 1995
- Accession Number
- ADA298834
Entities
People
- Ting-ting Lin
Organizations
- University of California