Multiprocessor Implementation of a Real-Time Celp Algorithm.

Abstract

The objective of this effort was to develop the methodology of transferring communication signal processing algorithms from a single processor (SUN Workstation) to multiple DSP processors TMS32OC4Os. The CELP (Code Excited Linear Prediction) voice compression algorithm was chosen for real time implementation of 3 processors. The algorithm operates at an output rate of 4800 bits per second with an input sampling rate of 8000 samples per second. Using efficient parallel processing algorithms (optimized to reduce the inter-processor communication time overhead) one can implement complicated communication functions such as the CELP algorithm on more than one processor and achieve real time performance. A block diagram description of the CELP algorithm has been developed using the Signal Processing Worksystem (SPW), a block oriented design tool from the Alta Group of Cadence to generate optimized code for a VMEbus based network of TM5320C40 processors. The CELP algorithm is based on the U.S. Federal Standard 1016. Data transfers between the processors is achieved by using the C40 processors' high speed communication ports and concurrent multi channel DMA transfer capability. The approach frees the CPU of burdensome interprocessor communication functions.

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Document Details

Document Type
Technical Report
Publication Date
Nov 01, 1996
Accession Number
ADA319761

Entities

People

  • Glenn Prescott
  • Hari N. Chakravarthula
  • Sinivas Sivaprakasam
  • Timouthy Johnson

Organizations

  • University of Kansas

Tags

DTIC Thesaurus Topics

  • Algorithms
  • Compression
  • Data Compression
  • Data Transmission
  • Multiprocessors
  • Parallel Computing
  • Parallel Processing
  • Processing Equipment
  • Sampling
  • Signal Processing
  • Standards

Fields of Study

  • Computer science
  • Engineering

Readers

  • Educational Psychology
  • Parallel and Distributed Computing.
  • Radio communications and signal processing.