Technological Development for Interfacing Parallel Access Memories to Parallel Computers.

Abstract

During this AASERT program, we have carried out the fabrication and evaluation of high speed receiver circuits implemented with this technology. To demonstrate the providing a bandwidth of 9GHz and an 8x8 III-V active-pixel sensor array with 285 MHz operation, In the following we present a complete characterization of this smart pixel technology, including the S- and Y-parameters extraction for the typical devices implemented by this technology.

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Document Details

Document Type
Technical Report
Publication Date
Mar 15, 1999
Accession Number
ADA362650

Entities

People

  • Sadik Esener

Organizations

  • University of California, San Diego

Tags

Communities of Interest

  • Advanced Electronics
  • Sensors

DTIC Thesaurus Topics

  • Amplifiers
  • Bandwidth
  • Capacitance
  • Circuits
  • Computers
  • Detectors
  • Diodes
  • Equivalent Circuits
  • Extraction
  • Field Effect Transistors
  • Flip Chips
  • High Electron Mobility Transistors
  • Materials
  • Modulators
  • Modules (Electronics)
  • Optoelectronic Devices
  • Pin Diodes

Readers

  • Electronics Engineering
  • Integrated Circuit Design and Technology.