Analysis of Ultra-High Speed, High Temperature Superconductor (HTS) Digital Circuits
Abstract
The purpose of this research was to determine the expected yields and bit error rates of HTS digital circuits operated at tens of gigahertz at various temperatures. This was done by using device parameters from TRW, Conductus, and Northrup Grumman for state-of-the-art devices. The circuits studied included two rapid-single-flux-quantum (RSFQ) T flip-flop circuits. One (with 14 Josephson junctions) included estimated undesirable parasitic inductances and other was assumed free of parasitics. We also analyzed a three-stage counter made of a cascade of the T flip-flops with parasitics with 38 junctions. We conducted Monte Carlo simulations and evaluated the bit-error rates (BER) at various temperatures. Yield calculations were made for operation at a number of multi-gigahertz frequencies. For higher frequency operation, the results improved strongly with higher assumed products of critical current and normal-state resistance (lcRn). For 50 GHz operation with lcRn = 0.5 mV, we compared the yield for a T flip-flop with that of the three-stage counter (70% vs. 34%). Bit-error-rate calculations suggest that operating temperature must be <20-30 K for a BER <10^-6.
Document Details
- Document Type
- Technical Report
- Publication Date
- Jan 18, 2000
- Accession Number
- ADA373697
Entities
People
- Theodore Van Duzer
Organizations
- University of California, Berkeley