Georgia Tech GT-VNUC VLSI Design Verification Document
Abstract
There are eleven Georgia Tech VLSI designs in the AHAT Program. Each of these designs has been produced by Georgia Tech using the Genesil Silicon Compiler. Each design has passed the design verification process at Silicon Compiler Systems I Mentor Graphics and each has been fabricated in a bulk CMOS process (fabrication of certain chips was not complete when this document was released). Each of the Georgia Tech designs listed in Table 1 is being delivered to USASDC and to the Harris Corporation for conversion and fabrication in a rad-hard process. The program under which this work is done is AHAT (Advanced Hardened Avionics Technology). This document includes design information for the Georgia Tech non-uniformity compensation chip, GT-VNUC.
Document Details
- Document Type
- Technical Report
- Publication Date
- Jul 05, 1991
- Accession Number
- ADA393316
Entities
People
- Prem Pahlajrai
- Toshiro Kubota
Organizations
- Georgia Tech