Current Apertured Vertical Electron Transistor (CAVET)
Abstract
We have demonstrated the first GaN current aperture vertical electron transistor (CAVET). A 2 micrometer thick GaN:Si drain region followed by a 0.4 micrometer GaN:Fe insulating layer and an 800 Angstrom unintentionally doped GaN cap were grown by MOCVD on a c-plane sapphire substrate. Channel apertures were etched, and a maskless regrowth was performed to grow conducting GaN inside the channel as well as to thicken the UID GaN above the insulating layer and add an AlGaN cap layer. C12 RIE was used to pattern the device mesa. Source, drain, and gate pads were then deposited. Devices with aperture widths ranging from 0.4 micrometer to 2 micrometer have been demonstrated. DC transistor characteristics were measured, and the effects of varying the aperture length and the gate overlap were investigated. Electrical characteristics of a device with a 0.6 micrometer aperture and a gate overlap of 2 micrometer are illustrated in Fig 2. This device had a source-drain saturation current of 430 mA/mm and an extrinsic transconductance of 100 mS/mm. Additionally, conditions for PEC etching of an InGaN layer for the CAVET illustrated in Fig 1d have been optimized.
Document Details
- Document Type
- Technical Report
- Publication Date
- Dec 01, 2001
- Accession Number
- ADA408527
Entities
People
- Umesh Mishra
Organizations
- University of California, Santa Barbara