Compiler Optimizations for Power-Aware Computing. Volume 2 of 2

Abstract

This final report summarizes work done on the DARPA funded project "Compiler Optimizations for Power Aware Computing." Volume I addresses methodologies invented that can be categorized as software based approaches, hardware based approaches and combined software/hardware based approaches. One of the software based approaches, data remapping, showed a 3.1X energy*delay reduction on a realistic example. One of the hardware based approaches, frequency/voltage scaling of second-level memory, showed a 1.3X energy*delay reduction on a realistic example. A combination of data remapping and frequency/voltage scaling of second level memory showed a 2.6X reduction in energy*delay but also showed the lowest power (energy/time) of any of the approaches considered. Volume II addresses realization of the world's first Wearable Motherboard or an intelligent garment for the 21st Century. The motherboard provides an extremely versatile framework for the incorporation of sensing, monitoring, and information processing devices.

Open PDF

Document Details

Document Type
Technical Report
Publication Date
Sep 01, 2003
Accession Number
ADA418764

Entities

People

  • Vincent J. Mooney Iii

Organizations

  • Georgia Tech Research Corporation

Tags

Communities of Interest

  • Biomedical
  • C4I
  • Energy and Power Technologies
  • Human Systems
  • Sensors

DTIC Thesaurus Topics

  • Air Force Research Laboratories
  • Computers
  • Electrical Circuits
  • Electrical Properties
  • Electrical Resistance
  • Engineering
  • Field Programmable Gate Arrays
  • Frequency
  • Information Processing
  • Integrated Circuits
  • Manufacturing
  • Materials
  • Military Research
  • Monitoring
  • Tensile Properties
  • Tensile Strain
  • Test Methods

Readers

  • Distributed Systems and Data Platform Development
  • Parallel and Distributed Computing.