PACE: Power-Aware Computing Engines
Abstract
This report describes the PACE project whose objective was to reduce the energy consumption of microprocessors by exploiting compile time knowledge to reduce run-time switching activity and to power down unneeded blocks. The project had two phases. The first phase focused on understanding and reducing power consumption within microprocessor components, such as caches, register files, and arithmetic units. Several new techniques were developed to reduce both switching and leakage power. The second phase developed a new energy-exposed microprocessor architecture, SCALE (Software-Controlled Architecture for Low Energy). SCALE is based on a new vector-thread architectural paradigm which unifies the vector and threaded execution models, to provide efficient execution of many forms of parallelism. The SCALE vector thread architecture and the detailed design are being pursued in other projects. The PACE project developed a variety of power saving techniques at both the micro architectural and instruction set level, several of which are being actively transferred to industry. Over a dozen conference papers and student theses have been published to distribute results to the research community.
Document Details
- Document Type
- Technical Report
- Publication Date
- Feb 01, 2005
- Accession Number
- ADA431169
Entities
People
- Krste Asanovic
Organizations
- Massachusetts Institute of Technology