Breaking the Memory Bottleneck with an Optical Data Path
Abstract
This paper demonstrates the capability of optical buses in enabling orders of magnitude greater bandwidth between the processor and off-chip memory in a uniprocessor computer system. Through a simulation-based performance analysis of a 1 GHz processor model, we provide a preliminary evaluation of the benefits of an optical processor-to-memory bus in both eliminating the bandwidth bottleneck and in reducing the impact of the increasing processor-to-memory latency gap. The optical technology is constructed of two-dimensional arrays of lasers and detectors bonded to silicon that provides high-speed optical I/O on-and-off chip. These chip-to-chip light paths may be designed using either rigid free-space optics or flexible fiber image guides. Utilizing the optical data path between the processor and memory provides significantly greater bandwidth with no appreciable latency penalty. We assess the performance impact of this architecture enhancement on a number of media applications. Overall we found that the increased bandwidth nearly eliminates the transfer time between processor and memory, effectively reducing degradation from off-chip memory latency by 50% on average. Additionally, substantial extra bandwidth remains for more bandwidth-intensive architectural options like aggressive latency hiding techniques and single-chip multiprocessors.
Document Details
- Document Type
- Technical Report
- Publication Date
- Jan 01, 2005
- Accession Number
- ADA436219
Entities
People
- Jason E. Fritts
- Roger D. Chamberlain
Organizations
- Washington University in St. Louis