Multidimensional Dataflow Graph Modeling and Mapping for Efficient GPU Implementation

Abstract

Multidimensional synchronous dataflow (MDSDF) provides an effective model of computation for a variety of multidimensional DSP systems that have static dataflow structures. In this paper, we develop new methods for optimized implementation of MDSDF graphs on embedded platforms that employ multiple levels of parallelism to enhance performance at different levels of granularity. Our approach allows designers to systematically represent and transform multi-level parallelism specifications from a common, MDSDF-based application level model. We demonstrate our methods with a case study of image histogram implementation on a graphics processing unit (GPU). Experimental results from this study show that our approach can be used to derive fast GPU implementations and enhance trade-off analysis during design space exploration.

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Document Details

Document Type
Technical Report
Publication Date
Oct 01, 2012
Accession Number
ADA570740

Entities

People

  • Chung-ching Shen
  • Gunasekaran Seetharaman
  • Kannappan Palaniappan
  • Lai-huei Wang
  • Shuvra S. Bhattacharyya

Organizations

  • University of Maryland

Tags

Communities of Interest

  • Ground and Sea Platforms

DTIC Thesaurus Topics

  • Air Force Research Laboratories
  • Case Studies
  • Computations
  • Digital Communications
  • Digital Signal Processing
  • Graphics
  • Graphics Processing Unit
  • Graphs
  • Histograms
  • Image Processing
  • Integrals
  • Parallel Computing
  • Parallel Processing
  • Platforms
  • Signal Processing
  • Specifications
  • Two Dimensional

Fields of Study

  • Computer science
  • Engineering

Readers

  • Database Systems and Applications
  • Graph Algorithms and Convex Optimization.
  • Radio communications and signal processing.

Technology Areas

  • Space