Fault Analysis-based Logic Encryption (Preprint)
Abstract
Globalization of the integrated circuit (IC) design industry is making it easy for rogue elements in the supply chain to pirate ICs, overbuild ICs, and insert hardware trojans. Due to supply chain attacks, the IC industry is losing approximately $4 billion annually. One way to protect ICs from these attacks is to encrypt the design by inserting additional gates such that correct outputs are produced only when specific inputs are applied to these gates. The state - of - the - art logic encryption technique inserts gates randomly into the design but does not necessarily ensure that wrong keys corrupt the outputs. Our technique ensures that wrong keys corrupt the outputs. We relate logic encryption to fault propagation analysis in IC testing and develop a fault analysis - based logic encryption technique. This technique achieves 50% Hamming distance between the correct and wrong outputs (ideal case) when a wrong key is applied. Furthermore, this 50% Hamming distance target is achieved using a smaller number of additional gates when compared to random logic encryption.
Document Details
- Document Type
- Technical Report
- Publication Date
- Nov 01, 2013
- Accession Number
- ADA617770
Entities
People
- Chi Zhang
- Garret S. Rose
- Huan Zhang
- Jeyavijayan Rajendran
- Ozgur Sinanoglu
- Ramesh Karri
- Youngok Pino
Organizations
- New York University