Design and Demonstration of RSFQ Processor Datapath for High Performance Computing

Abstract

The main goal of the project is designing in RSFQ technology a 20-GHz 8-bit-wide energy efficient processor datapath consisting of an 8-bit ALU, an 8x8-bit Register File, and an Instruction Decoder. We have had several project modifications resulted in additional tasks, such as the development of energy-efficient zero-static-power dissipation SFQ technology, the development of energy-efficient interface based on a low input voltage polarization modulating VCSELs, and the development of superconducting ferromagnetic Random Access Memory

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Document Details

Document Type
Technical Report
Publication Date
Sep 30, 2014
Accession Number
ADA623723

Entities

People

  • A.F. Kirichenko

Tags

Communities of Interest

  • Advanced Electronics
  • Energy and Power Technologies

DTIC Thesaurus Topics

  • Converters
  • Data Links
  • Digital Circuits
  • Digital Data
  • Distributed Bragg Reflectors
  • Electronics Industry
  • Energy Efficiency
  • Fabrication
  • High Performance Computing
  • Instruction Set Architecture
  • Lasers
  • Materials
  • Measurement
  • Photonic Crystals
  • Semiconductors
  • Test And Evaluation
  • Transmission Lines

Fields of Study

  • Physics

Readers

  • Integrated Circuit Design and Technology.
  • Parallel and Distributed Computing.