Area Efficient Cells for LagerIV's DPP Library

Abstract

Semi-custom design of high-performance VLSI processors has been demonstrated by the Berkeley VLSI-PLM chip using Mentor Graphics IDEA station, Cell station tools and NCR tools. To support semi-custom design using Berkeley VLSI tools such as LagerIV, we have developed a set of cells. These cells are designed with the goal of designing a high-performance VLSI Parallel Prolog Processor. They can be used in other designs such as DSP chips. Some of these cells complement those in LagerIV's DPP cell library. Others provide an area efficient replacement for the DPP cells.

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Document Details

Document Type
Technical Report
Publication Date
Aug 01, 1989
Accession Number
ADA632157

Entities

People

  • Georges E. Smine
  • Vason P. Srini

Organizations

  • University of California, Berkeley

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  • Advanced Electronics

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