Extraction of Topography Dependent Electrical Characteristics from Process Simulation Using SIMPL, with Application to Planarization and Dense Interconnect Technologies

Abstract

This project demonstrates the use of SIMPL-2 (SIMulated Profiles from the Layout) and SIMPL-DIX (Design interface with X windows) as an interface to other process and device simulators. An interface to RACPLE for analyzing topography dependent parasitic resistances and capacitances is implemented. Enhancements to SIMPL to call the non-planar etch simulation capabilities of SAMPLE are also presented. These integrated CAD tools are applied to a patterned photoresist planarization process, and to VLSI Hopfield neural networks. It is found that the patterned photoresist planarization process shows a relatively high tolerance to reasonable misalignments. VLSI neural networks show significant topography dependent RC parasitic delays which increase as the square of the number of neurons. Based on experience gained as a result of this work, several suggestions for the future of SIMPL are offered.

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Document Details

Document Type
Technical Report
Publication Date
Jun 08, 1989
Accession Number
ADA637168

Entities

People

  • Edward W. Scheckler

Organizations

  • University of California, Berkeley

Tags

Communities of Interest

  • Advanced Electronics

DTIC Thesaurus Topics

  • Capacitance
  • Computer Programs
  • Computer Science
  • Computer-Aided Design
  • Computers
  • Content Addressable Memory
  • Data Management
  • Databases
  • Electrical Engineering
  • Electrical Properties
  • Integrated Circuits
  • Lists (Data Structures)
  • Misalignment
  • Neural Networks
  • Resistance
  • Simulations
  • Simulators

Readers

  • Integrated Circuit Design and Technology.
  • Nanofabrication and Microfabrication.
  • Neural Network Machine Learning.

Technology Areas

  • AI & ML
  • AI & ML - Neural Networks