Integrated Circuits with Immunity to Single Event Effects

Abstract

The present invention is an electronic structure having a buffer layer with a short average carrier lifetime, at least about 1000 A thick with an upper face, and an integrated circuit disposed over the upper face of the buffer layer, where this integrated circuit would otherwise be susceptible to soft errors, due to its configuration, its clock speed, its use environment, or a combination of these factors. In a preferred embodiment, the preferably high recombination rate buffer layer is an LT GaAs or GaAs:Er buffer layer.

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Document Details

Document Type
Technical Report
Publication Date
May 31, 1996
Accession Number
ADD018877

Entities

People

  • Dale McMorrow
  • Todd R. Weatherford
  • Walter Curtice

Organizations

  • United States Department of the Navy

Tags

Communities of Interest

  • Advanced Electronics
  • Space

DTIC Thesaurus Topics

  • Circuits
  • Clocks
  • Computer Simulations
  • Computers
  • Cosmic Rays
  • Electronics
  • Environment
  • Field Effect Transistors
  • High Energy
  • Integrated Circuits
  • Inventions
  • Ions
  • Laser Pulses
  • Low Temperature
  • Materials
  • Radiation
  • Semiconductors

Readers

  • Electrical Engineering
  • Integrated Circuit Design and Technology.
  • Semiconductor Device Technology

Technology Areas

  • Microelectronics
  • Microelectronics - Graphene